Junctionless Fet

Posted : admin On 1/29/2022

Unlike conventional MOSFETs, junctionless field-effect transistors (JLFETs) contain no metallurgical junctions, so they are simpler to process and less costly to manufacture.JLFETs utilize a gated semiconductor film to control its resistance and the current flowing through it. Junctionless MOSFETs have a number of advantages over the traditional ones in terms of simplicity of design, manufacturing technology and reducing the.

Standard Dataset

Citation Author(s):
Cheng-Kuei Lee, Sen Yin, Jin-Yu Zhang, Zuo-Chang Ye,Yan Wang nad Zhi-ping Yu
Submitted by:
Sen Yin
Last updated:
Thu, 11/08/2018 - 10:34
DOI:
10.21227/m6xf-3898
License:
Categories:
Keywords:
junctionless (JL), SOI hybrid P/N fin channel JL thin film transistor (SOI-H-JL), double layers SOI-H-JL (SOI-DH-JL)
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Abstract

This research examined the electrical characteristicsof a conventional junctionless silicon-on-insulator (SOI-JL) and aSOI hybrid P/N fin channel JL thin film transistor (SOI-H-JL)using a simulation with gate lengths from 60 nm to 10 nm. Theinterface location of the SOI-H-JL has a depletion region of aparallel channel, which influences the effective thickness of thechannel. The threshold voltage can be adjusted by changing theconcentration of the substrate. Better electrical characteristicsand higher transconductance can be obtained under the shortchannel when compared with the conventional SOI-JL. Althoughthe hybrid structure has better electrical characteristics, thelarger gate capacitance results in the delay time excessively longas a defect, which can be improved by thickening the raisedsource/drain area. The circuit performance is evaluated bybuilding up an inverter using aforementioned devices.

This research examined the electrical characteristicsof a conventional junctionless silicon-on-insulator (SOI-JL) and aSOI hybrid P/N fin channel JL thin film transistor (SOI-H-JL)using a simulation with gate lengths from 60 nm to 10 nm. Theinterface location of the SOI-H-JL has a depletion region of aparallel channel, which influences the effective thickness of thechannel. The threshold voltage can be adjusted by changing theconcentration of the substrate. Better electrical characteristicsand higher transconductance can be obtained under the shortchannel when compared with the conventional SOI-JL. Althoughthe hybrid structure has better electrical characteristics, thelarger gate capacitance results in the delay time excessively longas a defect, which can be improved by thickening the raisedsource/drain area. The circuit performance is evaluated bybuilding up an inverter using aforementioned devices.

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Double Gate Junctionless Fet

Cheng-Kuei Lee, Sen Yin, Jin-Yu Zhang, Zuo-Chang Ye,Yan Wang nad Zhi-ping Yu, August 6, 2018, 'An Investigation of the Scalability of a 3D Stacked Hybrid P/N Layer and Vertical Gate SOI Junctionless FET', IEEE Dataport, doi: https://dx.doi.org/10.21227/m6xf-3898.
@data{m6xf-3898-18,
doi = {10.21227/m6xf-3898},
url = {https://dx.doi.org/10.21227/m6xf-3898},
author = {Cheng-Kuei Lee; Sen Yin; Jin-Yu Zhang; Zuo-Chang Ye;Yan Wang nad Zhi-ping Yu },
publisher = {IEEE Dataport},
title = {An Investigation of the Scalability of a 3D Stacked Hybrid P/N Layer and Vertical Gate SOI Junctionless FET},
year = {2018} }
Junctionless Fet
TY - DATA
T1 - An Investigation of the Scalability of a 3D Stacked Hybrid P/N Layer and Vertical Gate SOI Junctionless FET
AU - Cheng-Kuei Lee; Sen Yin; Jin-Yu Zhang; Zuo-Chang Ye;Yan Wang nad Zhi-ping Yu
PY - 2018
PB - IEEE Dataport
UR - 10.21227/m6xf-3898
ER -
Cheng-Kuei Lee, Sen Yin, Jin-Yu Zhang, Zuo-Chang Ye,Yan Wang nad Zhi-ping Yu. (2018). An Investigation of the Scalability of a 3D Stacked Hybrid P/N Layer and Vertical Gate SOI Junctionless FET. IEEE Dataport. https://dx.doi.org/10.21227/m6xf-3898
Cheng-Kuei Lee, Sen Yin, Jin-Yu Zhang, Zuo-Chang Ye,Yan Wang nad Zhi-ping Yu, 2018. An Investigation of the Scalability of a 3D Stacked Hybrid P/N Layer and Vertical Gate SOI Junctionless FET. Available at: https://dx.doi.org/10.21227/m6xf-3898.
Cheng-Kuei Lee, Sen Yin, Jin-Yu Zhang, Zuo-Chang Ye,Yan Wang nad Zhi-ping Yu. (2018). 'An Investigation of the Scalability of a 3D Stacked Hybrid P/N Layer and Vertical Gate SOI Junctionless FET.' Web.

Junctionless Tunnel Fet

1. Cheng-Kuei Lee, Sen Yin, Jin-Yu Zhang, Zuo-Chang Ye,Yan Wang nad Zhi-ping Yu. An Investigation of the Scalability of a 3D Stacked Hybrid P/N Layer and Vertical Gate SOI Junctionless FET [Internet]. IEEE Dataport; 2018. Available from : https://dx.doi.org/10.21227/m6xf-3898
Cheng-Kuei Lee, Sen Yin, Jin-Yu Zhang, Zuo-Chang Ye,Yan Wang nad Zhi-ping Yu. 'An Investigation of the Scalability of a 3D Stacked Hybrid P/N Layer and Vertical Gate SOI Junctionless FET.' doi: 10.21227/m6xf-3898

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Permalink: http://ieee-dataport.org/documents/investigation-scalability-3d-stacked-hybrid-pn-layer-and-vertical-gate-soi-junctionless

DOI Link: https://dx.doi.org/10.21227/m6xf-3898

Junctionless Tunnel Fet

Short Link: http://ieee-dataport.org/1082

Junctionless Fet

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