Verilog Syntax Cheat Sheet

Posted : admin On 1/29/2022
  1. Shift Operator , Verilog Example Create shift registers, shift left, shift right in your FPGA or ASIC. The shift operator in Verilog is used to shift data in a variable. The left hand side of the operator contains the variable to shift, the right hand side of the operator contains the number of shifts to perform.
  2. MIPS Cheat Sheet. Saved by Rusty Shackleford. Assembly Language Cheat Sheets Programming Meant To Be Coding Chocolate Cube Reading Computer Programming.
  3. Verilog HDL Quick Reference Guide 2 1.0 New Features In Verilog-2001 Verilog-2001, officially the “IEEE 1364-2001 Verilog Hardware Description Language”, adds several significant enhancements to the Verilog-1995 standard. Attribute properties (page 4). Generate blocks (page 21). Configurations (page 43).

This enables compilation for system verilog source files.v: use this flag to indicate which verilog files are part of the library and thus be compiled if needed.timescale: can be used to specify how the abstract delay units in their design map into real time units e.g.

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Here you find a complete list of all the features contained in V3S, including a short description, VHDL and Verilog/SystemVerilog support, and the corresponding default Visual Studio Shortcut. This list not only contains V3S specific commands and functions, but also standard features natively supported by Visual Studio which you might find handy.
Verilog and SystemVerilog support is still in an early phase. It will be enhanced and extended continuously.

Coding

FeatureDescription Default Shortcut vhdlv/sv
RenamingAllows semantically correct renaming of signals, variables, functions, entities, etc.F2
Find all referencesFinds all references of a given identifier in the entire project.Shift+F12
Naming rules checkChecks if the symbols (signals, functions, etc) obey the configured naming conventions
Syntax HighlightingCode highlighting according to VHDL 2008 syntax: Keywords, symbols, strings, identifiers, etc.
Semantic HighlightingCode highlighting according to semantic analysis: Types, signals, ports, constants, etc. See Syntax Highlighting for details!
Type-time Error CheckingOn-the-fly error checking and highlighting. Output in Visual Studio's Error Output Window.
Code Completion/AutocompleteContext sensitive code completion (for defined signals, types, entites, etc.).Ctrl+Space
List SymbolsShows a list of all defined items (also refer to Code Completion).Ctrl+J
Block Selection KeyboardHolding Alt+Shift while moving the cursor with the cursor keys uses the very handy block/column-selection mode of Visual Studio.Alt+Shift+Cursors
Block Selection MousePressing Alt while selecting code with the mouse uses the very handy block/column-selection mode.Alt+Mouse
Smart IndentationCan be deactivated temporarily with Shift and permanently in Preferences. Automatically sets the indent of new code lines according to formatting rules.
Smart Indentation for PasteCan be deactivated temporarily with Shift and permanently in Preferences. Automatically sets the indent of pasted code according to formatting rules.
Increase IndentIncreases the indent of the currently selected code lines.Tab
Decrease IndentDecreases the indent of the currently selected code lines.Shift+Tab
Quickinfo/TooltipUseful information (e.g., type, default value, location, etc.) of the underlying item are displayed.Ctrl+K+I
Expression EvaluatorSimple constant expressions are automatically evaluated and the result is displayed in the tooltip. Selected expressions are evaluated as well. Also simple string expressions can be resolved.
Number ConversionNumbers, Bitstring, Binary String, etc. are converted to decimal, hex, binary formats and displayed as quickinfo. Floats are displayed as IEEE single/double precision floating point number.
Comment LinesComments the selected lines (line commenting).Ctrl+K+Ctrl+C
Uncomment LinesUncomments the selected lines (line commenting).Ctrl+K+Ctrl+U
Code Snippets (Expansion)Opens a list of all available Expansion-Code-Snippets (snippets that insert new code). Select one to insert the respective snippet into the source code.Ctrl+K+Ctrl+X
Code Snippets (Surround)Opens a list of all available Surround-Code-Snippets (snippets that surround selected code). Make a text selection, then choose a snippet to surround the selected code with the respective snippet.Ctrl+K+Ctrl+S
Code SnippetsInserts the code snippet with the respective link/shortcut [*]. The following shortcuts are defined:
Expansion Snippets:
  • a+Tab: Architecture
  • ar+Tab: Assert-Report with severity
  • r+Tab: Report with severity
  • const+Tab: Constant
  • c+Tab: Component (lists available entities)
  • ea+Tab: Entity and Architecture
  • e+Tab: Entity
  • fl+Tab: For-Loop
  • fld+Tab: For-Loop (Range: downto)
  • flt+Tab: For-Loop (Range: to)
  • ig+Tab: if-generate statement
  • fg+Tab: for-generate statement
  • cg+Tab: case-generate statement
  • w+Tab: While-Loop
  • f+Tab: Function
  • i+Tab: Instance (lists available entites and components)
  • if+Tab: If-Then statement
  • ife+Tab: If-Then-Else statement
  • ifei+Tab: If-Then-Elsif-Else statement
  • phb+Tab: Package Head and Body
  • ph+Tab: Package Head
  • pb+Tab: Package Body (lists available package heads)
  • p+Tab: Procedure
  • rec+Tab: Record type definition
  • sp+Tab: Synchronous Process (lists possible signals for clock and reset)
  • ssp+Tab: Simple synchronous process (clock, but no reset)
  • ap+Tab: Asynchronous Process
  • cs+Tab: Case Statement (lists signal of enumeration type for state-machine implementation)
  • o+Tab: (others => '0')
  • oo+Tab: (others => '...')
  • sig+Tab: Signal declaration of base types: integer, natural, std_logic, boolean, std_logic_vecotor
  • sigslv+Tab: Signal declaration for std_logic_vector type
  • var+Tab: Variable declaration of base types: integer, natural, std_logic, boolean, std_logic_vecotor
  • varslv+Tab: Variable declaration for std_logic_vector type
  • sl+Tab: std_logic
  • slv+Tab: std_logic_vector()
  • u+Tab: unsigned()
  • s+Tab: signed()
  • tu+Tab: to_unsigned()
  • ts+Tab: to_signed()
Surrounding Snippets (xxx is the selected text):
  • std_logic_vector(xxx)
  • unsigned(xxx)
  • signed(xxx)
  • to_unsigned(xxx)
  • to_signed(xxx)
  • if(xxx)
*+Tab
Code Snippets (Forward)When in snippet insertion mode, use TAB to move to the next field (and probably show the suggestions list).Tab
Code Snippets (Backward)When in snippet insertion mode, use SHIFT+TAB to move to the previous field (and commit the current value for previous, and probably show the suggestions list).Shift+Tab
Line DuplicationWhen nothing is selected, these shortcuts duplicate the current line.Ctrl+C+Ctrl+V
Library ViewOpens a view which shows the current project's library hierarchy.
Hierarchy ViewOpens a view which shows the current project's design hierarchy.
Create TestbenchOpens a dialog where you can easily create a testbench for an arbitrary entity.
Parameter HelpOpens a tooltip with parameter help for the current function/procedure/component/entityCtrl+Shift+Space
Code FormattingFormats the document or the selection according to your preferences. An (optional) popup-window is shown where settings can be adjusted on the flyCtrl+K+Ctrl+F

Navigation

FeatureDescription Default Shortcut vhdlv/sv
Quick SearchShows a dialog to quickly search for project files and global symbolsShift+Shift
Find all referencesFinds all references of a given identifierShift+F12
Navigate ForwardMove forward to an already visited locationCtrl+Shift+-
Navigate BackwardMove backward to a previously visited locationCtrl+-
Code FoldingCollapse certain code blocks for better overview and navigation efficiency (processes, function, entities, classes, methods, records, instances, ...)
Navigation BarsNavigate between design units inside a file, and between code blocks inside a design unitCtrl+F2
Tuple HighlightingMatching of tuples: Brace matching, if-then-elsif-else-end, case-when-end, process-begin-end, etc. matching
Goto DeclarationJumps to the declaration of the current itemCtrl+F12
Goto DefinitionJumps to the definition of the current item (if different from its declaration)F12

Project Setup

FeatureDescription Default Shortcut vhdlv/sv
New Project WizardStarts the V3S New Project Wizard. Within some clicks, you can create an
  • Empty project
  • Sample project
  • 'Hello World' project
  • Import an existing Altera Quartus Project
  • Import an existing Xilinx Project (xise, xpr)
Ctrl+Shift+N
Virtual FoldersVirtual Folders help to organize your project, especially for files outside the project folder. You can only add files as links into virtual folders.
Linked FoldersLinked Folders allow you to link physical folders (using absolute path only!). Upon adding a linked folder, V3S can automatically import all contained files for you.
Add New ItemThere are two predefined templates: Add new VHDL Code File, and add new VHDL Library FileCtrl+Shift+A
Add Existing ItemOpens the dialog for adding exsting items to the project. Use 'Add as Link' for files outside the project directoryShift+Alt+A
Link FilesYou have the option to add files as link to your project only. Choose 'Add Existing Item', and click the small arrow next to the 'OK'-button, then choose 'Add as Link'
Code Statistics per FileOn the HDL files' property page (right-click file in solution explorer, select 'Properties'), there are some basic code statistics. The items are
  • Code lines
  • Comment lines
  • Empty lines
  • Total lines
Project-Wide StatisticsOn the project's property page (right-click project in solution explorer, select 'Properties'), there are some basic code statistics for all files (except IEEE default libraries) of the project. The items are
  • Code lines
  • Comment lines
  • Empty lines
  • Total lines
File PropertiesEach HDL file has associated file properties specific for V3S. The items are
  • Content type: Defines the type of the respective code file (Verilog, SystemVerilog, VHDL, Text, ...)
  • Library: Defines the VHDL library to which the file belongs. Default is 'work'
  • Notifcation Level: Defines the types of errors which will be displayed in the Error Output Window
  • Parsing Options: Let's you define whether to fully parse the file (which might be slow) or not
Alt+Return

Preferences

FeatureDescription Default Shortcut vhdlv/sv
Custom Syntax ColoringYou can define custom colors for all VHDL syntax elements like keywords, symbols, attributes, signals, constants, ...
Color PresetsI have assembled a number of color presets here for your convenience. There is a special preset for users of the dark theme
NotificationsHere you can adjust the notification levels for all available code checks
FormattingHere you can configure your prefered formatting styles (indenting, newlines, etc.)
LicensingHere you can review and setup your license
Naming ConventionsHere you can import/export your project's naming convention rules
VersionHere you can review your current version and check for updates
BasicsGeneral V3S settings
Language BasicsGeneral Language specific (VHDL/Verilog/SystemVerilog) V3S settings
Edit TemplatesAllows you to edit snippet, testbench, and new file templates

Others

FeatureDescription Default Shortcut vhdlv/sv
Productivity Power ToolsProductivity Powertools from Microsoft are an excellent and free enhancement for Visual Studio, and they work fine with V3S. I am using them as well, and I wouldn't wanna miss them ever again
Highlight all occurrencesAlso from Microsoft, also free, also very, very useful

For simple designs the major steps are:

  1. Compile the design
  2. Run the Simulation
  3. Generate Code Coverage Report

Compiling Verilog design using VCS

Included Options

  • -cm coverage-type: specifies the type of coverage information to collect. The line, tgl, cond, fsm and path options enable statement (line), toggle, condition, FSM, and path coverage respectively. Any combination of coverage can be enabled simultaneously using the + sign e.g. -cm cond+line enables conditional and line coverage.
  • -cm_line contassign: monitor continuous assignments for line coverage
  • -cm_cond allops+anywidth+event: monitor non-logical operators, of any width, and always block sensitivity expressions for condition coverage
  • -cm_noconst: try to automatically ignore constant expressions and unreachable statements
    for line and condition coverage
  • +lint=all: turns on all verilog warnings
  • +v2k: tells VCS to handle Verilog-2001 features, include this option if you are using those features
  • -PP: turns on support for using the VPD trace output format
  • -debug_all option allows to run the interactive DVE tool and use steps to debug the design
  • -l file_name: logs the compiler messages to given file name
  • -f file_name: tells VCS to read source files from the given file

Few optional arguments

Cheat
  • -sverilog: include this options if system verilog source files are also present. This enables compilation for system verilog source files.
  • -v: use this flag to indicate which verilog files are part of the library and thus be compiled if needed.
  • -timescale: can be used to specify how the abstract delay units in their design map into real time units e.g. -timescale=1ns/10ps

During compilation a subdirectory named csrc is created to store the files generated by compilation. This directory includes:

  • Makefile for the compilation process
  • Object files from the compilation. These object files are linked to create the simv executable.
  • Intermediate C or Assembly source files.

Incremental Compilation

The source files are compiled on module-by-module basis. Incremental compilation means that if we run the vcs command again, only the modules that have changed after the last compilation are recompiled. VCS compares the modules in the source file to the descriptor information in the generated files from the last compilation, if a module’s contents are different from what VCS recorded in the last compilation, VCS recompiles the module.

Compile time options that affect incremental compilation all begin with -M.

Running the Simulation

For text based output use:

For debugging with DVE GUI use:

For Generating code coverage information run as:

Generating code coverage reports using VCS URG

For generating code coverage report in html form use the following command

To generate code coverage report in text form add the extra options as

A directory named urgReport will be created in current directory. This directory contains all the generated reports.

References

Verilog Syntax Cheat Sheet Free

  • VCS Quickstart
  • VCS User Guide